Title :
An all implanted self-aligned enhancement mode n-JFET with Zn gates for GaAs digital applications
Author :
Sherwin, M.E. ; Zolper, J.C. ; Baca, A.G. ; Shul, R.J. ; Howard, A.J. ; Rieger, D.J. ; Klem, J.F. ; Hietala, Vincent M.
Author_Institution :
Sandia Nat. Labs., Albuquerque, NM, USA
fDate :
7/1/1994 12:00:00 AM
Abstract :
An all implanted self-aligned n-channel JFET fabrication process is described where Zn implantation is used to form the p/sup +/ gate region. A refractory metal (W) gate contact is used to allow subsequent high temperature activation of the self-aligned Si source and drain implant. 0.7 μm JFET´s have a maximum transconductance of 170 mS/mm with a saturation current of 100 mA/mm at a gate bias of 0.9 V. The p/sup +//n homojunction gate has a turn on voltage of 0.95 V at a current of 1 mA/mm. The drain-source breakdown voltage is 6.5 V. Microwave measurements made at a gate bias of 1 V show an fT of 19 GHz with an fmax of 36 GHz. These devices show promise for incorporation in both DCFL and complementary logic circuits.
Keywords :
III-V semiconductors; field effect integrated circuits; gallium arsenide; integrated logic circuits; ion implantation; junction gate field effect transistors; semiconductor doping; solid-state microwave devices; tungsten; zinc; 0.7 micron; 170 mS/mm; 19 GHz; 36 GHz; 6.5 V; DCFL; GaAs digital applications; GaAs:Si; GaAs:Zn; W gate contact; W-GaAs; Zn gates; complementary logic circuits; drain-source breakdown voltage; enhancement mode; fabrication process; high temperature activation; implanted self-aligned device; n-JFET; n-channel JFET; p/sup +/ gate region; p/sup +//n homojunction gate; refractory metal gate contact; self-aligned Si drain implant; self-aligned Si source implant; Gallium arsenide; Gate leakage; Implants; Ion implantation; MESFETs; Parasitic capacitance; Temperature; Transconductance; Voltage; Zinc;
Journal_Title :
Electron Device Letters, IEEE
