Abstract :
An associative memory system using push-down or first-in first-out (FIFO) lists as its basic building elements is described. With the development of large-scale integration technology (LSI), it is expected that devices with regular repetitive structure and high gate/interconnection ratio can be manufactured at extremely low cost. Push-down and FIFO evidently belong to that category. The logic design of a push-down and a FIFO list memory are first described. Then, with some additional control logic, it is shown that they can be converted to an associative memory.
Keywords :
Associative memory, counter, first-in first-out large-scale intergration, push-sown, shift register.; Adders; Associative memory; Costs; Counting circuits; Equations; Fast Fourier transforms; Large scale integration; Logic design; Parallel processing; Shift registers; Associative memory, counter, first-in first-out large-scale intergration, push-sown, shift register.;
