• DocumentCode
    1108818
  • Title

    Self-aligned half-micrometer Silicon MASFET´s with metallic amorphous Silicon gate

  • Author

    Sakaue, Masahiro ; Murase, Katsumi ; Amemiya, Yoshihito

  • Author_Institution
    NTT Atsugi Electrical Communications Laboratories, Atsugi-shi, Kanagawa Pref., Japan
  • Volume
    33
  • Issue
    7
  • fYear
    1986
  • fDate
    7/1/1986 12:00:00 AM
  • Firstpage
    997
  • Lastpage
    1004
  • Abstract
    Ternary metallic amorphous silicon (a-Si-Ge-B), having a high barrier height feature with crystalline semiconductors is applied to the gate metal of Si MESFET´s. A submicrometer gate length is successfully fabricated using a self-aligned technology and a conventional photolithography. A large transconductance above 130 mS/mm under the normally-OFF state and a small standard deviation of threshold voltage less than 11 mV are realized for a 0.5-µm gate-length device across a 4-in-diameter wafer. A minimum delay time of 114 ps/gate with an associated switching energy of 1.6 pJ and a minimum switching energy of 3.3 fJ with a delay time of 26 ns/gate are attained by a 21-stage ring oscillator with E/R direct-coupled FET logic circuits.
  • Keywords
    Amorphous silicon; Crystallization; Delay effects; FETs; Lithography; MESFETs; Ring oscillators; Switching circuits; Threshold voltage; Transconductance;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1986.22605
  • Filename
    1485822