A ring array processor architecture for highly parallel dynamic time warping

A ring array architecture is studied on a hardware algorithm and a control scheme for dynamic time warping (DTW) processing, in order to achieve real-time speech recognition. For developing a practical DTW processor, the key factors are to reduce the number of processing elements (PE\´s) in the array architecture and to maintain highly efficient concurrency and high throughput. Regular data and control flow is achieved by using a ring network, where every constituent PE uses parallel and pipelined operations on the data. Regular and continuous DTW processing, even for a variety of treated data volume, is realized with a novel control scheme based on "tags" and "status flags" attached to the data, thus indicating data attributes. This control scheme permits a simple control structure to be achieved for the array system. The efficiency and throughput expected for the ring array architecture is then compared to orthogonal array architecture.