Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs

Interposer-based 2.5-D integrated circuits (ICs) are seen today as a first step toward the eventual industry adoption of 3-D ICs based on through-silicon vias (TSVs). The TSVs and the redistribution layer (RDL) in the silicon interposer, and micro-bumps in the assembled chip must be adequately tested for product qualification. We present an efficient interconnect-test solution that targets TSVs, RDL wires, and micro-bumps for shorts, opens, and delay faults. The proposed test technique is fully compatible with the IEEE 1149.1 Standard. To reduce test cost, we also present a test-path design and scheduling technique that minimizes a composite cost function based on test time and the design-for-test overhead in terms of additional TSVs and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a single test path. We present simulation results to demonstrate the effectiveness of fault detection, and synthesis results to evaluate the hardware cost per die relative to the IEEE 1149.1 Standard. We also present test-path design and test-scheduling results to highlight the effectiveness of the optimization technique.