• DocumentCode
    1109536
  • Title

    Optimised design of ECL gates with power constraint

  • Author

    Grasso, A.D. ; Palumbo, G.

  • Author_Institution
    Dipt. di Ingegneria Elettrica Elettronica e dei Sistemi, Univ.´´ di Catania, Italy
  • Volume
    40
  • Issue
    19
  • fYear
    2004
  • Firstpage
    1169
  • Lastpage
    1170
  • Abstract
    A design strategy for the optimisation of the propagation delay of low-power emitter coupled logic gates is discussed. These results can be applied when there is a power constraint and the level of available current is lower than the optimum. The strategy is independent of the process used and simple to design, avoiding the trial-and-error approach based on simulations. The use of the procedure is illustrated and validated by SPICE simulations on a two input multiplexer, using a bipolar process the npn transistor of which has an fT of 20 GHz.
  • Keywords
    SPICE; bipolar logic circuits; delays; emitter-coupled logic; logic design; logic gates; multiplexing equipment; 20 GHz; ECL gate design; SPICE simulations; bipolar process; circuit optimisation; low power emitter coupled logic gates; npn transistor; power constraint; propagation delay; two input multiplexer;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20045930
  • Filename
    1336629
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1109536