Optimised design of ECL gates with power constraint

A design strategy for the optimisation of the propagation delay of low-power emitter coupled logic gates is discussed. These results can be applied when there is a power constraint and the level of available current is lower than the optimum. The strategy is independent of the process used and simple to design, avoiding the trial-and-error approach based on simulations. The use of the procedure is illustrated and validated by SPICE simulations on a two input multiplexer, using a bipolar process the npn transistor of which has an f_T of 20 GHz.