DocumentCode :
1109633
Title :
A 5–6 GHz 1-V CMOS Direct-Conversion Receiver With an Integrated Quadrature Coupler
Author :
Chen, Hsiao-Chin ; Wang, Tao ; Lu, Shey-Shi
Author_Institution :
Nat. Taiwan Univ., Taipei
Volume :
42
Issue :
9
fYear :
2007
Firstpage :
1963
Lastpage :
1975
Abstract :
This paper describes a novel monolithic low voltage (1-V) CMOS RF front-end architecture with an integrated quadrature coupler (QC) and two subharmonic mixers for direct-down conversion. The LC-folded-cascode technique is adopted to achieve low-voltage operation while the subharmonic mixers in conjunction with the QC are used to eliminate LO self-mixing. In addition, the inherent bandpass characteristic of the LC tanks helps suppression of LO leakage at RF port. The circuit was fabricated in a standard 0.18-mum CMOS process for 5-6 GHz applications. At 5.4 GHz, the RF front-end exhibits a voltage gain of 26.2 dB and a noise figure of 5.2 dB while dissipating 45.5 mW from a 1.0-V supply. The achieved input-referred DC-offset due to LO self-mixing is below -110.7 dBm.
Keywords :
CMOS integrated circuits; MMIC mixers; coupled circuits; low-power electronics; radio receivers; CMOS direct-conversion receiver; LC-folded-cascode technique; LO self-mixing; RF front-end architecture; frequency 5 GHz to 6 GHz; gain 26.2 dB; integrated quadrature coupler; low-voltage operation; monolithic low voltage CMOS; noise figure 5.2 dB; power 45.5 mW; size 0.18 mum; subharmonic mixers; voltage 1 V; CMOS process; Gain; Low voltage; Low-noise amplifiers; Noise figure; Radio frequency; Radiofrequency integrated circuits; System-on-a-chip; Topology; Transceivers; Direct-down conversion; LO self-mixing; RFIC; folded cascode; front-end; homodyne receivers; low voltage operation; low-noise amplifiers; mixers;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2007.903041
Filename :
4295181
Link To Document :
بازگشت