A New Approach to the Fault Location of Combinational Circuits

Author

Su, Stephen Y H ; Cho, Yun-chung

Author_Institution

Department of Electrical Engineering, University of Southern California

Issue

1

fYear

1972

Firstpage

21

Lastpage

30

Abstract

A systematic approach to the location of a single failure in a combinational logic network is presented. The method utilizes only the required tests and needs no fault table. The structure of the logic network is taken into consideration when selecting the tests to be applied. For tree networks, we start from the gate that generates a primary output and sequentially trace back through the stages of the network according to a fixed set of rules. At each stage we either locate the fault or determine the direction of the trace.

Keywords

Combinational logic, diagnosis algorithms, diagnostic test generation, error diagnosis, fault location, logic circuit diagnosis, sensitized faults, testing, tree networks, undistinguishable faults.; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault diagnosis; Fault location; Input variables; Logic circuits; Logic testing; Switching circuits; Combinational logic, diagnosis algorithms, diagnostic test generation, error diagnosis, fault location, logic circuit diagnosis, sensitized faults, testing, tree networks, undistinguishable faults.;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/T-C.1972.223427

Filename

1672020