Title :
Low-Capacitance and Charge-Shared Match Lines for Low-Energy High-Performance TCAMs
Author :
Mohan, Nitin ; Sachdev, Manoj
Author_Institution :
Boston Design Center, Boxborough
Abstract :
Emerging high-speed lookup-intensive applications are demanding ternary content addressable memories (TCAMs) with large word-sizes, which suffer from lower search speeds due to larger match line capacitance. Therefore, low-energy high-performance design techniques are needed, which improve the search speeds of TCAMs without increasing their power consumption. In this paper, we present a cell-level comparison logic and a charge-shared match line scheme. Both schemes reduce search time and energy in TCAMs. Measurement results of the above schemes, implemented in 0.18-mum CMOS technology, show a search time reduction of 42% and 11%, and a search-energy reduction of 25% and 9%, respectively.
Keywords :
CMOS memory circuits; content-addressable storage; logic design; CMOS technology; cell-level comparison logic; charge recycling; charge-shared match lines; low-capacitance match lines; low-energy high-performance TCAM; match line capacitance; size 0.18 mum; ternary content addressable memories; Associative memory; CADCAM; CMOS logic circuits; CMOS technology; Capacitance; Computer aided manufacturing; Energy consumption; Multilevel systems; Recycling; Time measurement; Content addressable memory (CAM); charge recycling; high performance; low energy; ternary content addressable memory (TCAM);
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.903089
