Title :
Generation of Fault Tests for Linear Logic Networks
Author :
Breuer, Melvin A.
Author_Institution :
Department of Electrical Engineering, University of Southern California
Abstract :
In this note we study the problem of fault detection in linear logic networks. We introduce the concept of error vectors that indicate how the effect of a fault propagates through a network. These vectors allow one to identify redundancies in the network as well as calculate the output of the network given a fault and an input. Problems related to fault diagnosis and the detection of multiple faults are also considered.
Keywords :
Fault detection, fault diagnosis, linear networks, logical redundancies.; Automata; Circuit faults; Circuit synthesis; Fault detection; Fault diagnosis; Logic testing; Pediatrics; Sequential circuits; Switching circuits; Vectors; Fault detection, fault diagnosis, linear networks, logical redundancies.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/T-C.1972.223433
