A new self-aligned well-isolation technique for CMOS devices

This paper presents the development of a new well-isolation technique for advanced CMOS LSI´s. The technique comprises narrow deep trench fabrication utilizing undercut, in addition to silicon-oxide cap formation, which leaves a cavity. The predominant feature of this technique is that well isolation self-aligned to the well region is realized utilizing the trench fabrication technique. Additionally, no crystal defects are observed around the well isolation even after 1000°C annealing following silicon-oxide cap formation. Since the well isolation produced also prevents the latchup phenomenon from occurring due to its depth, this technique enables the CMOS device dimensions to be considerably reduced.