Simulation of a word recognition system on two parallel architectures

The use of two parallel architectures, a single-instruction-stream, multiple-data-stream (SIMD) machine and a VLSI processor array, to implement an isolated word recognition system is examined. SIMD and VLSI processor array algorithms are written for each of the components of the recognition system. The component parallel algorithms are simulated along with two complete recognition systems, one composed of SIMD algorithms and other composed of VLSI processor array algorithms. The simulations show that a SIMD machine with 100 processing elements, each based on an 8-MHz MC68000, can perform isolated word recognition over a large vocabulary in real time. The VLSI processor array simulations show that an array using 51 cells, each containing a 12-MHz Intel 8051, can recognize speech in real time over a small vocabulary. The simulation revealed certain architectural features that can enhance the overall performance of the speech system