A modified lightly doped drain structure for VLSI MOSFET´s

A new n-MOS LDD-like device structure (the J-MOS transistor) is proposed. Its design, simulation, and fabrication are studied in this paper, n-channel MOSFET´s with Leffbelow 2 µm suffer from high-field effects that must be overcome to secure reliable 5-V operation. LDD structures alleviate these effects, but their reliability is better than that of conventional MOSFET´s only if the n^-regions have a peak doping density above 1 × 10¹⁸cm^-3. To overcome this limitation and to allow constant voltage scaling for devices into the submicrometer regime, the J-MOS structure uses a series drain JFET to drop part of the supply voltage. Both 2-D device simulations and experimental results are presented to demonstrate the operation of this device and its potential for applications requiring reliable submicrometer device operation under maximum supply voltage. The major experimental findings are that the J-MOS structure can sustain 5-V operation even for submicrometer effective channel lengths. As has been the case with all LDD-like structures, improved device reliability has been achieved at the expense of some performance. However, the advantages of keeping 5-V operation in micrometer-sized devices may outweigh this performance loss.