AT2-optimal Galois field multiplier for VLSI

VLSI designs for Galois field multipliers, which are central in many encoding and decoding procedures for error-detecting and error-correcting codes, are presented. An AT²-optimal Galois-field multiplier based on AT ²-optimal integer multipliers for a synchronous VLSI model is exhibited. Galois field multiplication is done in two steps. First two polynomials (of degree n-1) over Z_p are multiplied, and then the resulting polynomial is reduced modulo a fixed irreducible polynomial (of degree n). Multiplication of polynomials is done by discrete Fourier transform (DFT). For p=2, the procedure is more involved for Z _p[x] than for Z[x]. An extension to the case of variable p is included and some open problems are stated