A design approach for self-diagnosis of fault-tolerant clock synchronization

A general design approach for self-diagnosis of faulty clocking modules in a fault-tolerant clock synchronization (FTCS) system is presented. The approach is based on a statistical testing method. The major advantages are better self-stability control and lower overhead. The design methodology includes a self-diagnosis algorithm to transform a partially self-stabilizing clocking system into a self-stabilizing one. Compound to partially self-stabilizing clocking systems, this approach offers several advantages. First, the self-stabilization of the FTCS system is achieved with the support of repair techniques. Second, the system availability for performing synchronization and coordinated actions is controlled by the designer. Third, the transformation overhead is kept to a minimum. Finally, the approach is not limited to the situation in which single clock failure occurs between successive diagnoses