On serial-input multipliers for two´s complement numbers

The author shows that a multiplier already proposed by T. Rhyne and N.R. Strader (see ibid., vol.C-35, p.896-901 (1986)) for unsigned numbers can be used for two´s complement numbers as well, provided only that the content of the input registers is held constant, after the introduction of the operand´s sign bits, for a number of clock periods equal to the operand´s length. The result is derived by the properties of sign-extended two´s complement numbers. The known multiplier includes a linear array of (5, 3) parallel counters and a set of three static registers for the internal carriers. It is shown that a logically equivalent multiplier can be built using two linear arrays of full adders and two carry registers. In a faster circuit, an additional carry register is required