Error-Control Techniques for Logic Processors

A new error-control technique for logic processors is given. The proposed technique uses Reed-Muller codes (RMC´s). The design scheme given has better efficiency than the schemes proposed earlier. The improved efficiency is obtained by relaxing a basic assumption originally made by Elias. Furthermore, it is shown that the efficiency of the proposed scheme asymptotically approaches the maximum efficiency achievable by a practical though restricted class of error-control schemes. Reliability of the proposed scheme is studied.