DocumentCode
1110650
Title
Sign extension bit minimisation algorithm for multi-bit coded multiplier structures for DSP applications
Author
Poornaiah, D.V.
Author_Institution
Indian Telephone Ind. Ltd., Bangalore, India
Volume
32
Issue
16
fYear
1996
fDate
8/1/1996 12:00:00 AM
Firstpage
1454
Lastpage
1456
Abstract
A novel algorithm for minimising the sign extension bits involved in the design of VLSI multi-bit coded multiplier and multiplier-accumulator arithmetic modules is described. Design examples are presented to illustrate the flexibility of the proposed algorithm
Keywords
VLSI; digital arithmetic; digital signal processing chips; minimisation; multiplying circuits; DSP applications; VLSI multi-bit coded multiplier; multi-bit coded multiplier structures; multiplier-accumulator arithmetic modules; sign extension bit minimisation algorithm;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19961007
Filename
511890
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