Title :
Parasitic coupling in 3D technologies
Author :
Bouvier, S. ; Belleville, M. ; McDevitt, M. ; Lecarval, G.
Author_Institution :
CEA, Centre d´´Etudes Nucleaires de Grenoble, France
fDate :
8/1/1996 12:00:00 AM
Abstract :
The influence of a conducting line located below an SOI transistor is presented from a 3D integration perspective. Using numerical simulations, the authors analyse the behaviour of the back gate MOSFET, the parasitic bipolar transistor and the capacitive coupling for partially and fully depleted SOI transistors
Keywords :
MOS integrated circuits; integrated circuit technology; silicon-on-insulator; 3D integration technology; SOI transistor; back gate MOSFET; capacitive coupling; conducting line; numerical simulation; parasitic bipolar transistor; parasitic coupling;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19960965
