• DocumentCode
    1111653
  • Title

    Error-correction and crosstalk avoidance in DSM busses

  • Author

    Patel, Ketan N. ; Markov, Igor L.

  • Author_Institution
    Qualcomm Corp., San Diego, CA, USA
  • Volume
    12
  • Issue
    10
  • fYear
    2004
  • Firstpage
    1076
  • Lastpage
    1080
  • Abstract
    Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on long, adjacent bus wires can lead to timing violations and logic faults. At the same time, system-level interconnects have also become more susceptible to other less predictable forms of interference such as noise induced by power grid fluctuations, electromagnetic interference, and alpha-particle radiation. Previous work has treated these systematic and nonsystematic forms of noise separately. We propose to make system-level interconnects more robust using encoding that simultaneously addresses error-correction requirements and crosstalk noise avoidance. This is more efficient than satisfying these requirements separately. We give algorithms for obtaining optimal encodings and present a practical class of codes called boundary-shift codes. We evaluate the overhead of our method, and make comparisons to using error-correction with simple shielding.
  • Keywords
    VLSI; crosstalk; electromagnetic interference; encoding; error correction; error correction codes; error detection; integrated circuit design; integrated circuit interconnections; integrated circuit noise; integrated logic circuits; logic circuits; shielding; system buses; DSM busses; VLSI design; aggressive process scaling; alpha particle radiation; boundary shift codes; bus wires; clock rates; crosstalk avoidance; crosstalk noise; electromagnetic interference; error-correction; logic faults; optimal encoding; power grid fluctuations; robust interconnects; shielding; system-level interconnects; timing violations; Clocks; Crosstalk; Electromagnetic interference; Electromagnetic radiative interference; Encoding; Logic; Power system interconnection; Timing; Very large scale integration; Wires;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2004.827565
  • Filename
    1336852