Effects of speculation on performance and issue queue design

Current trends in microprocessor designs indicate increasing pipeline depth in order to keep up with higher clock frequencies and increased architectural complexity. Speculatively issued instructions are particularly sensitive to increases in pipeline depth. In this brief, we use load hit speculation as an example, and evaluate its cost effectiveness as pipeline depth increases. Our results indicate that as pipeline depth increases, speculation is more essential for performance but can drastically alter the utilization of pipeline resources, particularly the issue queue. We propose an alternative, more cost-effective design that takes into consideration the different issue queue utilization demands without degrading overall processor performance.