DocumentCode
1111991
Title
Complete Test Sets for Logic Functions
Author
Reddy, Sudhakar M.
Author_Institution
Department of Electrical Engineering, University Iowa
Issue
11
fYear
1973
Firstpage
1016
Lastpage
1020
Abstract
The problem of designing fault detecting test sets from the functional description rather than the structural description of the networks realizing the logic function is studied. The concept of an expanded truth table for logic functions is introduced. It is proved that the set of minimal true vertices and maximal false vertices of the expanded truth table constitutes a test set to detect any number of stuck-at-faults in a network belonging to a class of restricted networks, called unate gate networks. It is further indicated that even in the presence of redundancies in the network, the test sets given remain valid.
Keywords
Complete test sets, expanded truth table, fault detecting test sets, logic networks, multiple stuck-at-faults, restricted gate networks, stuck-at-faults, unate gate networks.; Cities and towns; Fault detection; Input variables; Inverters; Logic functions; Logic testing; Redundancy; Complete test sets, expanded truth table, fault detecting test sets, logic networks, multiple stuck-at-faults, restricted gate networks, stuck-at-faults, unate gate networks.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1973.223638
Filename
1672231
Link To Document