Syntactic translation and logic synthesis in Gatemap

Gatemap is a logic synthesis system for digital integrated-circuit design, which automatically generates gate-level circuit implementations from behavioural Ella descriptions. These behavioural descriptions may contain a variety of arithmetic, relational and logical operators expressed using the Ella hardware design and description language. A process of syntactic translation is used to convert this input into minimised Boolean equations. Various logic synthesis techniques are then used to implement these equations using technology-specific logic gates. The final output is a variety of netlists for input to gate-level simulators and layout tools. Currently, two CMOS gate-array and one CMOS cell-based process technologies are supported, though further CMOS technologies could be addressed via the provision of the appropriate libraries.