DocumentCode
1112379
Title
On designing robust testable CMOS combinational circuits
Author
Gupta, B. ; Malaiya, Y.K. ; Min, Y. ; Rajsuman, R.
Author_Institution
Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
Volume
136
Issue
4
fYear
1989
fDate
7/1/1989 12:00:00 AM
Firstpage
329
Lastpage
338
Abstract
The potential invalidation of two-pattern tests for detecting stuck-open faults in CMOS combinational circuits has been studied from a functional point of view. Two methods of testable realisations avoiding the problem are presented. A new type of two-level testable realisation is proposed in which both stuck-open and stuck-short faults can be detected. In both the methods, valid test patterns are applied at the inputs and the logic responses are observed at the output. Finally, multilevel realisations of combinational functions have been considered in which all stuck-short faults are three-pattern testable and all stuck-open faults are two-pattern testable.
Keywords
CMOS integrated circuits; combinatorial circuits; logic testing; logic responses; robust testable CMOS combinational circuits; stuck-open faults; stuck-short faults; three-pattern testable; two-pattern testable; two-pattern tests;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings E
Publisher
iet
ISSN
0143-7062
Type
jour
Filename
29518
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