• DocumentCode
    1112418
  • Title

    An Augmented Iterative Array for High-Speed Binary Division

  • Author

    Cappa, Maurus ; Hamacher, V. Carl

  • Author_Institution
    Collins Radio Company
  • Issue
    2
  • fYear
    1973
  • Firstpage
    172
  • Lastpage
    175
  • Abstract
    An augmented iterative array for binary division (IAD), is described. It uses carry-save reduction and carry-look-ahead principles to achieve high speed. Logic cost and speed comparisons with two other design techniques are presented. An 8-bit prototype model that operates in under 500 ns has been built from commercially available high-speed MSI TTL integrated circuits to verify the feasibility of the IAD scheme.
  • Keywords
    Division network, iterative array, nonrestoring division.; Costs; Digital arithmetic; Fabrication; Fast Fourier transforms; High speed integrated circuits; Integrated circuit modeling; Iterative algorithms; Logic arrays; Logic design; Prototypes; Division network, iterative array, nonrestoring division.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/T-C.1973.223680
  • Filename
    1672273
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1112418