A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with fermat numbers

A quadratic-polynominal Fermat residue number system (QFNS) was used to compute complex integer multiplications in [1]. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this correspondence, a new type of Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-pw technology.