DocumentCode :
1112611
Title :
Parallel processing architectures for rank order and stack filters
Author :
Lucke, Lori E. ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Volume :
42
Issue :
5
fYear :
1994
fDate :
5/1/1994 12:00:00 AM
Firstpage :
1178
Lastpage :
1189
Abstract :
Many architectures have been proposed for rank order and stack filtering. To achieve additional speedup in these structures requires the use of parallel processing techniques such as pipelining and block processing. Pipelining is well understood but few block architectures have been developed for rank order and stack filtering. Block processing is essential for additional speedup when the original architecture has reached the throughput limits caused by the underlying technology. A trivial block structure simply repeats a single input, single output structure to generate a multiple input, multiple output structure. Therefore the architecture can achieve speedups equal to the number of multiple outputs or the block size. However, unlike linear filters, the rank order and stack filter outputs are calculated using comparisons. It is possible to share these comparisons within the block structure and thus substantially reduce the size of the block structure. The authors introduce a systematic method for applying block processing to rank order filters and stack filters. This method takes advantage of shared comparisons within the block structure to generate a block filter with shared substructures whose complexity is reduced by up to one-third compared to the original filter structure times the block size. Furthermore, block processing is important for the generation of low power designs. A block structure can trade its increased speedup for a throughput equal to the original single output architecture but with a significantly lower power requirement. The power reduction in the trivial block structures is limited by the power supply voltage. They demonstrate how block structures with shared substructures allow them to continue decreasing the power consumption beyond the limit imposed by the supply voltage
Keywords :
digital filters; filtering and prediction theory; parallel architectures; block architectures; block processing; low power designs; multiple input multiple output structure; parallel processing architectures; pipelining; power consumption; power reduction; power supply voltage; rank order filters; single input single output structure; speedup; stack filters; throughput; Bandwidth; Clocks; Energy consumption; Filtering; Nonlinear filters; Parallel processing; Pipeline processing; Power generation; Sorting; Voltage;
fLanguage :
English
Journal_Title :
Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1053-587X
Type :
jour
DOI :
10.1109/78.295200
Filename :
295200
Link To Document :
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