Multiplier-free IIR filter realization using periodically time-varying state-space structure. II. VLSI architectures

Author

Ghanekar, Sachin ; Tantaratana, Sawasd ; Franks, Lewis E.

Author_Institution

Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA

Volume

42

Issue

5

fYear

1994

fDate

5/1/1994 12:00:00 AM

Firstpage

1018

Lastpage

1027

Abstract

In Part I of this paper, a multiplier-free realization for IIR filters based on periodically time-varying state-space (PTV-SS) systems was proposed. Each biquad unit of the given target filter is realized with a higher order PTV-SS system operating at a higher speed. The coefficients of the PTV-SS system are restricted to a few power-of-two values. Therefore, such a structure can be implemented using shift and accumulate operations. In this paper, nonsystolic as well as systolic architectures for VLSI implementations of the PTV-SS system are developed. Different architectures are obtained using different timings and locations of the shift-and-accumulate operations. The design process is illustrated for a fourth-order PTV-SS system

Keywords

VLSI; digital filters; state-space methods; systolic arrays; time-varying networks; VLSI architectures; accumulate operations; biquad unit; coefficients; fourth-order PTV-SS system; multiplier-free IIR filter; nonsystolic architectures; periodically time-varying state-space structure; shift operations; systolic architectures; Digital filters; Feedback; Finite impulse response filter; IIR filters; Narrowband; Pipeline processing; Process design; Time varying systems; Timing; Very large scale integration;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.295215

Filename

295215