ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism

Author

Zhan, Rouying ; Feng, Haigang ; Wu, Qiong ; Xie, Haolu ; Guan, Xiaokang ; Chen, Guang ; Wang, Albert Z H

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Inst. Technol., Chicago, IL, USA

Volume

23

Issue

10

fYear

2004

Firstpage

1421

Lastpage

1428

Abstract

On-chip electrostatic discharge (ESD) protection design is a challenging IC design problem. New computer-aided design (CAD) tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel smart parametric-checking mechanism and a new intelligent CAD tool, entitled ESD inspector, developed for full-chip ESD-protection circuitry-design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35-μm BiCMOS technology.

Keywords

BiCMOS integrated circuits; circuit layout CAD; electrostatic discharge; intelligent design assistants; system-on-chip; 0.35 micron; BiCMOS technology; CAD tools; ESD protection design prediction; ESD protection design verification; ESDInspector; IC design problem; circuitry design verification tool; computer-aided design; full-chip ESD-protection circuitry-design verification; layout verification; on-chip electrostatic discharge; parasitic ESD protection device; smart-parametric checking; BiCMOS integrated circuits; Bipolar transistor circuits; Design automation; Electric potential; Electrostatic discharge; Helium; Integrated circuit technology; Protection; Radiofrequency integrated circuits; Stress; ESD; ESD protection; ESDInspector; Electrostatic discharge; layout verification; parasitic ESD protection device;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2004.833613

Filename

1336952