DocumentCode :
1113109
Title :
An analog VLSI implementation of Hopfield´s neural network
Author :
Verleysen, Michel ; Jespers, Paul G A
Author_Institution :
Microelectron. Lab., Catholic Univ. of Louvain, Belgium
Volume :
9
Issue :
6
fYear :
1989
Firstpage :
46
Lastpage :
55
Abstract :
The basic requirements for electronic implementations of the fully connected Hopfield network are examined, highlighting the reasons why the authors regard analog implementations as more appropriate. Analog VLSI networks are then discussed, with particular reference to the selection of memory points and the design of the synapse, and experimental results are given. A test chip containing 14 neurons and 196 synapses is described.<>
Keywords :
VLSI; analogue computer circuits; linear integrated circuits; neural nets; parallel architectures; analog VLSI implementation; electronic implementations; fully connected Hopfield network; neural network; neuron cell; neurons; nonlinear neuronal functions; selection of memory points; synapse; synapses; Circuits; Computer networks; Hopfield neural networks; Multi-layer neural network; Nearest neighbor searches; Neural networks; Neurofeedback; Neurons; Output feedback; Very large scale integration;
fLanguage :
English
Journal_Title :
Micro, IEEE
Publisher :
ieee
ISSN :
0272-1732
Type :
jour
DOI :
10.1109/40.42986
Filename :
42986
Link To Document :
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