Analog VLSI synaptic matrices as building blocks for neural networks

Author

Rossetto, Olivier ; Jutten, Christian ; Herault, Jeanny ; Kreuzer, Igno

Author_Institution

Nat. Polytech. Inst. of Grenoble, France

Volume

9

Issue

6

fYear

1989

Firstpage

56

Lastpage

63

Abstract

An associative memory circuit that may let designers expand neural networks around a matrix of analog synapses is described. The architecture of the chip and its basic cell are discussed, and some SPICE simulation results are presented and compared with measures provided by the first prototype. In particular, the linearity and dynamic response of the complete chip, which includes an array of 25 synapses and two address decoders used for programming the weights, are examined.<>

Keywords

CMOS integrated circuits; VLSI; analogue computer circuits; analogue storage; content-addressable storage; linear integrated circuits; multiplying circuits; neural nets; CMOS chip; SPICE simulation; address decoders; analog VLSI synaptic matrices; analog synapses; associative memory circuit; dynamic response; multipliers matrix; neural networks; weights; Associative memory; Circuit simulation; Decoding; Dynamic programming; Linearity; Neural networks; SPICE; Semiconductor device measurement; Very large scale integration; Virtual prototyping;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.42987

Filename

42987