• DocumentCode
    1113181
  • Title

    A three-dimensional static RAM

  • Author

    Inoue, Y. ; Sugahara, K. ; Kusunoki, S. ; Nakaya, M. ; Nishimura, T. ; Horiba, Y. ; Akasaka, Y. ; Nakata, H.

  • Author_Institution
    Mitsubishi Electric Corporation, Itami, Japan
  • Volume
    7
  • Issue
    5
  • fYear
    1986
  • fDate
    5/1/1986 12:00:00 AM
  • Firstpage
    327
  • Lastpage
    329
  • Abstract
    A three-dimensional (3-D) 256-bit static random-access memory (RAM) with double active layers has been fabricated by using the laser recrystallization technique. Memory cells were located in a bottom active layer with an NMOS configuration and peripheral circuits were arranged in a top active layer with a CMOS configuration. Both active layers were connected by 112 via holes. The chip and cell sizes were 2.6 × 1.9 mm2and 50 × 70 µm2, respectively. The memory operation was observed with a supply voltage from 4 to 8 V. The shortest address access time of 42 ns was obtained at the supply voltage of 8 V.
  • Keywords
    CMOS memory circuits; Decoding; Large scale integration; MOS devices; Planarization; Random access memory; Read-write memory; Research and development; Silicon; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/EDL.1986.26389
  • Filename
    1486212