DocumentCode
1113191
Title
Synthesis of Diagnosable FET Networks
Author
Paige, Michael R.
Author_Institution
General Research Corporation
Issue
5
fYear
1973
fDate
5/1/1973 12:00:00 AM
Firstpage
513
Lastpage
516
Abstract
With the advent of field-effect transistor (FET) technology it has become practical and economical to employ complex functions as network primitives. This paper describes a synthesis procedure for diagnosable (all single and multiple faults can be detected) FET networks. A companion procedure for generating tests to detect all faults in the resulting network is also described. This methodology does not guarantee the minimality of the network, however, it is intuitively understandable and easy to apply.
Keywords
Fault diagnosis, FET network, irredundant function, network synthesis, single and multiple faults.; Boolean functions; FETs; Fault detection; Fault diagnosis; Hardware; Helium; Logic devices; Logic gates; Network synthesis; Testing; Fault diagnosis, FET network, irredundant function, network synthesis, single and multiple faults.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1973.223754
Filename
1672347
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