Title : 
Gigahertz logic gates based on InP-MISFET´s with minimal drain current drift
         
        
            Author : 
Pande, Krishna P. ; Fathimulla, Mohammed A. ; Gutierrez, D. ; Messick, L.
         
        
            Author_Institution : 
Allied Corporation, Columbia, MD
         
        
        
        
        
            fDate : 
7/1/1986 12:00:00 AM
         
        
        
        
            Abstract : 
Three-input AND/NOR logic gates based on 3-µm overlapping gate InP-MISFET technology were fabricated and clocked at 1 GHz. The logic gates showed a propagation delay of ∼500-700 pS/gate for a channel length of 1.5 µm. Such high-speed performance was obtainable as a result of a novel process that was used in the fabrication of the MISFET´s. The process included the saturation of InP surface with phosphorus vapor and growth of a P2OxN1-xinterfacial layer followed by the deposition of an SiO2gate insulator. MISFET´s that were utilized in the logic gates showed a channel mobility of ∼3700 cm2/V.s and less than 3-percent drain current drift.
         
        
            Keywords : 
Annealing; Circuits; Dielectric substrates; Fabrication; Indium phosphide; Logic devices; Logic gates; Metallization; Plasma immersion ion implantation; Sea surface;
         
        
        
            Journal_Title : 
Electron Device Letters, IEEE
         
        
        
        
        
            DOI : 
10.1109/EDL.1986.26418