Integrated electrical vernier to measure registration accuracy

A new high-speed integrated electrical test structure is developed to measure registration accuracy between a conductive layer and a insulating layer in a single chip. This structure utilizes a pair of digitally readable tapered comb (TC) patterns as a vernier. This eliminates measurement errors due to process variations such as resist pattern fluctuation or overetching. By incorporating transfer gate arrays and a shift register to sequentially address a desired position, a measurement speed of 500 µs/point is achieved.