Procedures for Eliminating Static and Dynamic Hazards in Test Generation

One problem associated with test generation algorithms for sequential circuits is that they often produce tests which, when applied to the circuit under test, create static and/or dynamic hazards which may invalidate the test. Usually, for static hazards, but not dynamic hazards, these situations can be predicted using a logic simulator. In this paper we present procedures which can be added to path sensitization test generation algorithms so that the resulting procedure will not produce tests which will be invalidated due to hazards. Incidental to this work is a new simulation technique for handling both static and dynamic hazards. The principal concepts behind this work deal with detecting when hazards are created in a circuit; propagating hazard status information related to a signal line through a circuit; detecting those conditions at flip-flop inputs which necessitate hazard free conditions; and finally, selecting test inputs so that all hazard free conditions are satisfied.