Title :
Easily Testable Two-Dimensional Cellular Logic Arrays
Author :
Saluja, Kewal K. ; Reddy, Sudhakar M.
Author_Institution :
Department of Electrical Engineering. University of Iowa
Abstract :
An algorithm to synthesize two-dimensional AND-EOR arrays is given. The design criterion chosen is to minimize the number of columns in the two-dimensional cellular arrays. It is also shown that And-Eor arrays, synthesized using the algorithm presented, can be modified such that 2n + 5 test vectors will detect any single fault in the array realizing an n-variable function with only one observable output. Furthermore, this test set is shown to be independent of the function being realized by the cellular array under test.
Keywords :
Cellular arrays, controllable inputs, fault detection, minimization algorithms for cellular arrays, single faults, stuck-at-faults.; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Logic arrays; Logic circuits; Logic design; Logic functions; Logic testing; Minimization; Cellular arrays, controllable inputs, fault detection, minimization algorithms for cellular arrays, single faults, stuck-at-faults.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/T-C.1974.223831
