Low-Power DT $\Delta \Sigma$ Modulators Using SC Passive Filters in 65 nm CMOS

A comparative design study of ultra-low-power discrete-time ΔΣ modulators (DT ΔΣMs) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive filter. Two design variants of 2nd-order ΔΣMs are analyzed and compared to a power-optimized standard active modulator (ΔΣM_AA). The first variant (ΔΣM_AP) employs an active filter in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less ΔΣM_PP) makes use of passive filters in both stages. For practical verification, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the ΔΣM_AA, ΔΣM_AP, and ΔΣM_PP achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 μW, 1.27 μW, and 0.92 μW, respectively, from a 0.9 V supply. Furthermore, the ΔΣM_PP can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.