Author :
Shikano, Hiroaki ; Ito, Masaki ; Onouchi, Masafumi ; Todaka, Takashi ; Tsunoda, Takanobu ; Kodama, Tomoyuki ; Uchiyama, Kunio ; Odaka, Toshihiko ; Kamei, Tatsuya ; Nagahama, Ei ; Kusaoke, Manabu ; Nitta, Yusuke ; Wada, Yasutaka ; Kimura, Keiji ; Kasahara,
Abstract :
This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamically reconfigurable processor (DRP) ACC cores in a preliminary evaluation of the HMCP architecture. The performance evaluation revealed that 54times AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1- 2 min.
Keywords :
audio coding; low-power electronics; memory architecture; microprocessor chips; speech codecs; system-on-chip; AAC-LC stereo encoding; SoC; accelerators; advanced audio codec-low complexity stereo coding; audio encoding; dynamically reconfigurable processor; embedded systems; frequency 300 MHz; frequency 600 MHz; general-purpose processors; heterogeneous multi-core architecture; heterogeneous multi-core processor; homogeneous processor cores; improved compiling efficiency; improved programming; low-power consumption; memory architectures; time 1 min to 2 min; Computer architecture; Data mining; Embedded system; Encoding; Frequency; Indium tin oxide; Memory architecture; Multicore processing; Parallel processing; Scheduling; AAC encoding; accelerator; dynamically reconfigurable processor; heterogeneous multi-core; parallel processing;
