• DocumentCode
    1114592
  • Title

    A self-aligned gate superlattice (Al,GA)As/n+-GaAs MODFET 5 × 5-bit parallel multiplier

  • Author

    Arch, D.K. ; Betz, B.K. ; Vold, P.J. ; Abrokwah, J.K. ; Cirillo, N.C., Jr.

  • Author_Institution
    Honeywell Physical Sciences Center, Bloomington, MN
  • Volume
    7
  • Issue
    12
  • fYear
    1986
  • fDate
    12/1/1986 12:00:00 AM
  • Firstpage
    700
  • Lastpage
    702
  • Abstract
    A 5 × 5-bit parallel multiplier circuit has been demonstrated with self-aligned gate superlattice (Al,Ga)As/n+-GaAs modulation-doped FET´s (MODFET´s). Multiplication times (gate delays) and corresponding power dissipations of 1.80 ns (73 ps/gate) at 0.43 mW/gate and 1.08 ns (43 ps/gate) at 0.75 mW/gate were measured at room temperature and 77 K, respectively. These are the shortest gate propagation delays ever reported for parallel multiplier circuits at room temperature or 77 K using any semiconductor IC technology.
  • Keywords
    Adders; Delay; Gallium arsenide; HEMTs; Logic circuits; MESFETs; MODFET circuits; Signal processing; Superlattices; Temperature;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/EDL.1986.26525
  • Filename
    1486348
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1114592