A model of current—Voltage characteristics in polycrystalline silicon thin-film transistors

An empirical model for the current-voltage characteristics of polycrystalline silicon thin-film transistors is presented. The model was constructed based on the premise that the potential barrier height at the grain boundary depends on both the gate and drain voltages. Polycrystalline silicon film transistors having a coplanar structure were fabricated. Measurements demonstrated excellent agreement with calculations for n-channel devices. In addition, carrier-trap density and grain-boundary mobility, which have strong influences on electrical characteristics, were obtained from this model.