A Computer Algorithm for the Synthesis of Memoryless Logic Circuits

Author

Cerny, Edward ; Marin, Miguel A.

Author_Institution

Department of Electrical Engineering, Loyola College

Issue

5

fYear

1974

fDate

5/1/1974 12:00:00 AM

Firstpage

455

Lastpage

465

Abstract

A method has been investigated for the synthesis of memoryless logical networks using a restricted repertoire of functional modules. The method is based on the reduced general solution to a generalized system of Boolean equations (BE) as applied to the decomposition of Boolean functions. The aim of the synthesis is to obtain the most constrained circuit having at most two levels of gating. The constraints take the form of single input variables or constant logic levels applied to the inputs of the first level gate. This is achieved by assembling a set of constraint equations which are then a part of the generalized system of BE. The method is then tested on some synthesis examples of single and multiple output functions in terms of the NAND and (WOS) modules.

Keywords

Boolean equations (BE), combinational logic synthesis, computer program, constraints on logical space, cost factor, functional decomposition, multilevel logic.; Assembly systems; Boolean functions; Circuit synthesis; Computer languages; Equations; Input variables; Logic circuits; Logic programming; Network synthesis; System testing; Boolean equations (BE), combinational logic synthesis, computer program, constraints on logical space, cost factor, functional decomposition, multilevel logic.;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/T-C.1974.223967

Filename

1672560