DocumentCode :
1115489
Title :
On Minimally Testable Logic Networks
Author :
Saluja, Kewal K. ; Reddy, Sudhakar M.
Author_Institution :
Department of Electrical Engineering, University of Iowa
Issue :
5
fYear :
1974
fDate :
5/1/1974 12:00:00 AM
Firstpage :
552
Lastpage :
554
Abstract :
A new technique to modify any logic network to facilitate diagnosis is given. By providing extra controllable inputs (at most six) and observable outputs it is shown that any number of stuck-at-faults in a logic network can be detected by applying only three tests. This number is believed to be minimal for networks using current technologies. Example of logic module that can be used to realize any logic function such that only two tests detect stuck-at-faults is also given.
Keywords :
Fault detection, fault location, stuck-at-faults.; Circuit faults; Circuit testing; Cities and towns; Electrical fault detection; Fault detection; Fault location; Logic functions; Logic gates; Logic testing; Sequential analysis; Fault detection, fault location, stuck-at-faults.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/T-C.1974.223981
Filename :
1672574
Link To Document :
بازگشت