DocumentCode
1115541
Title
A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n+-doped polysilicon
Author
Son, Nak-Jin ; Oh, Yongchul ; Kim, Wookje ; Jang, Se-Myeong ; Yang, Wouns ; Jin, Gyoyoung ; Park, Donggun ; Kim, Kinam
Author_Institution
Semicond. R&D Center, Samsung Electron. Co., Kyunggi-Do, South Korea
Volume
51
Issue
10
fYear
2004
Firstpage
1644
Lastpage
1652
Abstract
Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully developed. A unique and simple DRAM technology with dual-gate CMOSFET was realized using plasma-nitrided thin gate oxide and p+ poly gate formed by BF2 ion implanted compensation of in situ phosphorus (n+) doped amorphous silicon gate. Using this technology, boron penetration into the channel, gate poly depletion, and dopant interdiffusion between n+- and p+-doped WSix-polycide gates were successfully suppressed. In addition, a negatively biased word line scheme and a storage capacitor with laminated high-κ Al2O3 and HfO2 dielectrics were also developed to achieve mobile DRAM operating at 1.2 V with excellent performance and reliability.
Keywords
CMOS memory circuits; DRAM chips; MOSFET; integrated circuit reliability; ion implantation; semiconductor doping; silicon; 1.2 V; 100 nm; Al2O3; BF2 ion; HfO2; Si; WSi∞-polycide gates; boron penetration; dopant inter-diffusion; doped amorphous silicon gate; dual-gate CMOSFET; dual-poly gate technology; gate oxide reliability; gate poly depletion; in situ n+-doped poly silicon; laminated high-K dielectrics; low-power dynamic random access memory; mobile DRAM; mobile dynamic random access memory; negative word line; negatively biased word line scheme; p+ poly gate; plasma nitridation; plasma-nitrided thin gate oxide; retention time; situ phosphorus; storage capacitor; tungsten polycide; Amorphous silicon; Boron; CMOS technology; CMOSFETs; Capacitors; DRAM chips; Hafnium oxide; Manufacturing; Plasma materials processing; Random access memory; $ and $hbox HfO_2$ ; $hbox Al_2 hboxO_; CMOSFET; DRAM; NWL; dual-poly gate; gate oxide reliability; low-power dynamic random access memory; negative word line; plasma nitridation; retention time; tungsten polycide;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2004.835162
Filename
1337176
Link To Document