A new structure-oriented model for well resistance in CMOS latchup structures

A new analytical model has been developed to deal with the parasitic well resistance in CMOS structures. This model also provides a closed-form expression for the induced potential drop in the well due to the action of an emitter in the substrate, and is expressed in terms of the structure parameters in the well, the well sheet resistance, and the current density across the Well-substrate junction. Based on the developed model, the calculated potential drops for various structures have been compared with the experimental results and good agreement has been obtained. Furthermore, the steady-state collector current of an active parasitic lateral bipolar transistor, which is used to trigger the parasitic vertical bipolar transistor into the latchup, has been calculated using the developed model. The calculated triggering currents in excess of 1 mA have a maximum error of 20 percent when compared with the experimental results measured from various structures. This error may be improved by taking into account the accurate position-dependent well sheet resistance. Therefore, the developed model becomes an efficient design tool for protecting the devices in the well from being disturbed by an active emitter in the substrate.