Anomalous Ti SALICIDE gate to source/drain shorts induced by dry Si etch during TiSi2 local interconnect formation

A new failure mode was observed in a 0.5 μm version of the silicided amorphous-silicon contact and interconnect (SAC) technology. Massive PMOS gate to source/drain shorts were found. The cause is attributed to formation of Ti during the Si etch. The fluorinated Ti surface fails to form adequate TiN diffusion barrier during subsequent rapid thermal annealing (RTA) in N₂ or NH₃ ambient. Si diffuses from the polycrystalline Si gate and/or the p-type source/drain onto the spacer, reacts with Ti and forms resistive leakage paths. A blanket low-dose, low-energy As implant prior to Ti deposition corrects this problem without adversely changing device characteristics.