A simple EEPROM cell using twin polysilicon thin film transistors

Author

Cao, Mino ; Zhao, Tiemin ; Saraswat, Krishna C. ; Plummer, James D.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

15

Issue

8

fYear

1994

Firstpage

304

Lastpage

306

Abstract

A planar twin polysilicon thin film transistor (TFT) EEPROM cell fabricated with a simple low temperature (/spl les/600/spl deg/C) process is demonstrated in this work. The gate electrodes of the two TFT´s are connected to form the floating gate of the cell, while the source and drain of the larger TFT are connected to form the control gate. The cell is programmed and erased by Fowler-Nordheim tunneling. The threshold voltage of the cell can be shifted by as much as 8 V after programming. This new EEPROM cell can dramatically reduce the cost of production by reducing manufacturing complexity.<>

Keywords

EPROM; MOS integrated circuits; chemical vapour deposition; elemental semiconductors; integrated circuit technology; integrated memory circuits; silicon; thin film transistors; tunnelling; 600 C; EEPROM cell; Fowler-Nordheim tunneling; Si; floating gate; low temperature process; thin film transistors; threshold voltage; twin polysilicon TFTs; Active matrix liquid crystal displays; Annealing; Capacitance; Costs; EPROM; Electrodes; Nonvolatile memory; Temperature; Thin film transistors; Tunneling;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.296224

Filename

296224