Development of a new self-aligning contact technology

A self-aligning contact process (SACMOS) for MOS/VLSI technology is described. A new technique involving submerged implant into the source and drain is employed. This enables the enhanced oxidation of the previously heavily doped polysilicon gate compared to the more lightly doped source and drain. The implant also provides the source and drain extensions. During oxidation, silicon nitride pads protect all contacts. A noncritical masking and etching stage is used to yield contacts. The process uses two extra masking stages to produce self-aligned contacts to the source, drain, and gate of MOS transistors, yielding a significant reduction in the area required for contact regions and hence a greater packing density. A process verification chip illustrated that discrete transistors designed using the new process exhibited similar properties to conventionally designed devices. Also a 21-stage ring oscillator designed with a minimum dimension of 6 µm occupied 15 percent less space than a conventional device and operated at the same speed under similar bias conditions. Finally it is estimated that a ROM designed using the new process occupies 25 percent less space.