Domain Wall Coupling-Based STT-MRAM for On-Chip Cache Applications

This paper proposes a domain-wall-coupling-based magnetic device for high-speed and robust on-chip cache applications. The read and write current paths are magnetically coupled and electrically isolated, which significantly improves the reliability of the read and write operations. Our proposed device makes use of fast and energy-efficient domain wall motion for write operation. A complementary polarizer structure is used to achieve low-power, high-speed, and high-sensing margin read operations. A device-to-circuits simulation framework was also developed to evaluate our proposed multiterminal domain-wall-coupling-based spin-transfer torque (DWCSTT) magnetic random access memory (MRAM) cell. Compared with the conventional 1T-1MTJ STT-MRAM bit cell, the proposed DWCSTT bit cell achieves > 3.5× improvement in write power under iso-area and iso-write margin conditions, and 3× better sensing margin with low read power consumption and higher read disturb margin.