Title :
Synthesis and Comparison of Two´s Complement Parallel Multipliers
Author :
Gibson, J.A. ; Gibbard, R.W.
Author_Institution :
Department of Electrical Engineering, University of Canterbury
Abstract :
A machine word mathematical formulation is applied to analysis and synthesis of circuits for signed binary number multiplication. The circuits are related to each other and to contemporary circuit algorithms in the course of the syntheses and in a comparative discussion. Circuits with complemented multiplier/multiplicand (M̄) or complemented partial product word (P̄) corrections offer advantages in circuit symmetry and algorithmic structure.
Keywords :
Algorithm syntheses, full adder arrays, multiplier comparisons, parallel binary multiplication, two´s complement formulation.; Adders; Array signal processing; Circuit simulation; Circuit synthesis; Computational modeling; Concurrent computing; Digital signal processing; Electrons; Logic arrays; Signal processing algorithms; Algorithm syntheses, full adder arrays, multiplier comparisons, parallel binary multiplication, two´s complement formulation.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/T-C.1975.224117
